Memory chips comprise an array of memory cells which are interconnected by bitlines and wordlines. The word lines and bit lines are used to read and write binary values to each of the memory cells, where each of the memory cells represents a bit of information. Since each memory cell represents a bit of information and may be connected to other circuitry, it is desirable that the electrical and operational characteristics of all memory cells be consistent.
In time division multiplexed static random access memory (TD SRAM), one of the primary cycle time limiters is restoring a bit line (BL) during the read and write intracycle time period. During the intracycle time period, the BL needs to be restored to stabilize half selected (HS) cells for the write operation. Further, even in a selected cell (i.e., where the write operation takes place), the BL needs to be restored to prevent a write issue where both the true BL and complement BL are discharged to ground.